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  • by GLOBAL UNICHIP CORP. (GUC)
    Global Unichip Corp. (GUC), the Advanced ASIC Leader, will showcase Jotunn8, a next-generation data center AI inference processor developed by VSORA, at the TSMC Europe Technology Symposium. The post GUC Showcases VSORA’s Jotunn8 AI inference Processor at the TSMC Europe Technology Symposium appeared first on EE Times.
  • by Echo Zhao
    Huawei's answer to Moore's Law without EUV promises 14A performance by 2031. The post From Shrinking Transistors to Compressing Time: Deciphering Huawei’s τ Law appeared first on EE Times.
  • by Yashasvini Razdan
    The Singapore-based startup develops optical transceivers for the next generation of data center infrastructure. The post LightSpeed Photonics Targets AI Data Centers With 400-Gbps Near-Packaged Optical Interconnects appeared first on EE Times.
  • by EE Times China
    Action Technology, an IC design company, provides core technological support for hundreds of millions of consumer audio devices worldwide. The post You May Not Know Actions Technology, But You’ve Definitely “Heard” It appeared first on EE Times.
  • by Steve Mansfield-Devine
    However much you prototype and test your product designs, there will always be factors outside your direct control that have significant implications for the manufacturability, efficiency, reliability and expected lifespan of your final product. One of the most important of these is the quality of the PCBs you receive from your chosen fabrication house. Many […] The post Realising the Benefits of Quality Inspection Reports appeared first on EE Times.
  • by Bill Schweber
    The power and thermal issues of placing data centers in space are formidable. The post Data Centers in Space: A Brilliant Idea or Delusional? appeared first on EE Times.
  • by Pat Brans
    A $2 billion CHIPS Act package backs quantum hardware across major modalities, underscoring Washington’s view of quantum computing as strategic infrastructure. The harder task is turning that hardware into useful applications. The post U.S. Quantum Bet Puts Hardware First, But Utility Remains the Test appeared first on EE Times.
  • by Analog Devices and Arrow Electronics
    Date: Tuesday, June 30, 2026 Time: 15:00 CEST As the Space market evolves and accelerates, mission designers need space-capable electronics that balance performance, reliability, and affordability, without sacrificing speed to deployment.  Join this webinar where we’ll explore ADI’s approach to supporting New Space programs through our purpose-built screening flows: Commercial Space Low (CSL) and Commercial Space […] The post Commercial Space Screening Approach for Agile, High-Reliability Payloads appeared first on EE Times.
  • by Pablo Valerio
    Washington signals its intent to lead the quantum computing revolution with a $2 billion investment and equity stakes. The post U.S. Injects $2B into Quantum Computing Companies appeared first on EE Times.
  • by Nitin Dahad
    Co-optimization and collaboration were key themes at ITF World 2026, alongside imec’s Neuropixels 3.0 research and imec.ventures’ work with startups. The post Imec Says AI Scaling Needs More Orchestration Across Research, Design, Manufacturing appeared first on EE Times.
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  • by Linda Christensen
    SRAM-based LLM inference; semantics-aware memory hierarchy for LLM reasoning; large-scale 2D material transfer; RISC-V vector performance portability; morphological mask optimization; trustworthy GenAI for automotive systems; HW-native GPU compilers for ML production. The post Chip Industry Technical Paper Roundup: May 26 appeared first on Semiconductor Engineering.
  • by Jesse Allen
    Three approaches toward energy-harvesting displays. The post Research Bits: May 26 appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    Researchers from Stanford University and Google have published “ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions”. Abstract “Hyperscaler reports of silent data corruptions (SDCs)—presumed to be caused by silicon manufacturing defects—have motivated the development of functional tests for detecting defective CPUs and their use in hyperscaler fleet studies. Interestingly, all such tests seem… » read more The post Detecting Defect-Induced Silent Data Corruptions in CPUs (Stanford, Google) appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    A new technical paper, “Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory,” was published by researchers from University of Seoul and Samsung Electronics. “This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and… » read more The post Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung) appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    Researchers from Columbia University and IBM Research have released “HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip”. Abstract “Large language models (LLMs) are adopted for software and hardware design, yet these domains are still evaluated separately. Software benchmarks typically assume fixed hardware targets, while hardware benchmarks focus on component-level optimization without considering the full… » read more The post An Agent-Driven End-to-End HW-SW Co-Design Benchmark for Heterogeneous SoCs (Columbia, IBM) appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    Researchers from Grenoble INP – UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, and performance, they also introduce… » read more The post Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.) appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    Researchers from AMD released “CompPow: A Case for Component-level GPU Power Management”. Abstract “The ever increasing demand for ML-driven intelligence in a wide spectrum of domains has led to ubiquity of GPUs. At the same time, GPUs are notorious for their power consumption needs and often dominate power allocation in a typical ML datacenter. While… » read more The post Improving GPU Energy Efficiency With Component-Level Power Management (AMD) appeared first on Semiconductor Engineering.
  • by The SE Staff
    Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs. The post Chip Industry Week In Review appeared first on Semiconductor Engineering.
  • by Technical Paper Link
    A new technical paper, “SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving,” was published by researchers at Nvidia, with work done while at Groq. Abstract “The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV… » read more The post Large-scale, SRAM-based LLM Inference Deployment (Groq) appeared first on Semiconductor Engineering.
  • by Anders Blom
    Capturing important details without making calculations impractically expensive. The post Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling appeared first on Semiconductor Engineering.